The present invention relates to microelectronic components and fabrication of microelectronic components.
Numerous microelectronic components incorporate insulating or xe2x80x9cdielectricxe2x80x9d layers and conductors extending through such layers. The directions along the surfaces of the layers are commonly referred to as xe2x80x9chorizontalxe2x80x9d directions, whereas the direction through the layers is commonly referred to as the xe2x80x9cverticalxe2x80x9d or xe2x80x9czxe2x80x9d direction. The conductors extending through the layers are commonly referred to as z-direction conductors or xe2x80x9cviasxe2x80x9d. For example, a multilayer microelectronic circuit panel may include several dielectric layers. Each dielectric layer has conductors extending along one or both surfaces of the layer in horizontal directions and has vias extending through the layer to connect certain conductors on opposite sides of the panel with one another. Typically, such a multi-layer circuit is fabricated by a sequential process. Each dielectric layer is deposited on previously-formed dielectric layers and the processes needed to form the vias and the horizontal conductors are performed. Such a sequential build-up process suffers from numerous drawbacks, including significant loss of productivity caused by quality problems. If any defect occurs in formation of a later layer, the entire multi-layer structure must be discarded.
As taught in certain preferred embodiments of commonly assigned U.S. Pat. Nos. 5,367,764 and 5,282,312, multi-layer circuit panels can be fabricated using a parallel processing approach. In this approach, the various panels constituting the multi-layer structure are fabricated separately and then stacked together with interposers incorporating a curable dielectric material such as an epoxy and also incorporating masses of electrically conductive joining material such as solder extending through the interposer at predetermined locations. The stacked assembly is then cured as, for example, under heat and pressure. The dielectric material joins the circuit panels to one another and the electrically conductive material forms conductive pathways between conductors on the various panels. Because the individual panels can be tested prior to assembly, defects in the panel manufacturing process do not result in loss of the entire assembly. Also, as further explained in the aforementioned ""764 and ""312 patents, the individual panels can be selectively treated so that vertical connections between panels are made only at certain locations.
Other processes involving parallel production of multiple circuit panels and assembly in a stack are taught in certain preferred embodiments of co-pending, commonly assigned PCT Application PCT/US97/23948, published as International Publication WO 98/26476 and U.S. Pat. No. 5,590,460. As taught in certain preferred embodiments of the ""460 patent and ""948 PCT application, multiple circuit panels can be stacked and electrically interconnected with one another and mechanically engaging features on the circuit panels with features of conductive elements carried on interposer layers.
These approaches offer useful solutions to the encountered in fabrication of multi-layer problems. However, even with these improvements, the circuit panels typically still include vias extending through dielectric layers. Such vias commonly are formed by providing holes in the dielectric layers and depositing a conductive metal in the dielectric layers by processes such as electroless plating and electroplating. These processes work well with relatively large vias. However, it would be desirable to provide smaller vias so as to make the entire assembly more compact. It is difficult to form relatively small vias, such as circular vias having diameters less than about 60 microns and, more particularly, less than about 25 microns by plating.
Various proposals have been advanced for depositing conductive materials into holes to form vias by techniques other than plating. Cranston, et al., U.S. Pat. No. 3,562,009 shows a process for forming xe2x80x9cmetalized through-holesxe2x80x9d by positioning a metallic element at a lower surface of a substrate having a hole formed therein and directing a laser beam or electron beam from above the substrate through the open top end of the hole onto the metal, thereby evaporating the metal onto the walls of the hole. In other embodiments, this reference discloses directing a similar beam onto a mass of powdered material disposed within the hole. This method suffers obvious drawbacks as a production technique, including the need to direct a powerful beam sequentially onto various locations on the substrate and hold the beam at each location for a time sufficient to vaporize the material. Moreover, this method is useful only to process a single substrate at a time. Beilin, et al., U.S. Pat. No. 5,454,161 discloses metal organic chemical vapor deposition (xe2x80x9cMOCVDxe2x80x9d) of metal into openings of a dielectric layer. In the MOCVD process, the substrate is held in the reaction chamber so that openings of the holes are exposed to the interior of the reaction chamber. A metal-containing gaseous composition is introduced into the chamber. The composition decomposes to deposit metal in the open vias. Yamaguchi, et al., U.S. Pat. No. 5,589,668, discloses a similar process using vapor deposition methods such as evaporation, ion plating, or sputtering. In all of these processes, the substrate is held within a chamber so that openings of the vias are open to the interior of the substrate. Each substrate must be held within a relatively complex and expensive treatment apparatus for a time sufficient to build up the required metallic layer within its vias. Moreover, stacked substrates cannot be treated. U.S. Pat. No. 4,933,045 refers to metalization of vias by xe2x80x9cevaporation, sputtering or platingxe2x80x9d as assertedly xe2x80x9cwell-known in the artxe2x80x9d but does not offer further details of such processes. Despite these attempts to use vapor deposition for forming vias, there is still need for better useful and economical vias-forming process.
Another common problem encountered in fabrication of microelectronic assemblies is mounting and connecting one component to another. For example, a semiconductor chip or other microelectronic device typically must be connected to a circuit panel. As described in certain preferred embodiments of commonly assigned U.S. Pat. Nos. 5,148,265, 5,148,266 and 5,347,159, the contacts of a semiconductor chip may be electrically connected to terminals on a small circuit panel or connection component overlying a face of the chip itself. The terminals on the connection component in turn are connected to contact pads on a substrate such as a circuit panel. Desirably, the connection component is movable with respect to the chip to accommodate dimensional changes caused by thermal effects during manufacture and/or use. The connections between the chip contacts and the interposer can be made by various methods. For example, these connections can be made by wire-bonding or by techniques such as thermosonic or ultrasonic bonding of pre-fabricated leads on the interposer to the chip contacts. Further improvements in lead bonding are taught, for example, in U.S. Pat. Nos. 5,536,909, 5,787,581 and PCT International Publication 94/03036. These processes provide marked improvements in chip connection processes and in the resulting assemblies.
In a process known as flip-chip bonding, contacts on the chip are bonded directly to contact pads on a substrate such as a circuit board using solder balls. All of the contacts of the chip may be connected simultaneously. However, flip-chip bonding requires considerable spacing between contacts on the chip to accommodate the solder balls and suffers from other drawbacks including susceptibility to thermal stresses.
As described in U.S. Pat. No. 5,518,964, numerous connections on a semiconductor chip or wafer can be made simultaneously by superposing an element such as a dielectric substrate having leads thereon with the chip or wafer bonding tip ends of the leads to the contacts on the chip and moving the element away from the chip or wafer so as to deform the leads. The resulting structure provides compensation for thermal effects and provides a high-reliability interconnection with the chip. Nonetheless, it would be desirable to provide even further improvements in methods for connecting components to one another.
Kim, U.S. Pat. No. 5,407,864 proposes mounting a chip on one surface of a circuit panel so that the contacts of the chip face down onto a top surface of a circuit board. The contacts on the chip are aligned with through-holes extending through the circuit board, to the bottom surface thereof. A metal is deposited through the openings of the through-holes at the bottom surface, as by sputtering, screening, electroplating or evaporation, so that the deposited metal forms conductive extensions of the chip contacts extending through the holes to conductors on the circuit board. This method suffers from the obvious drawback that holes must extend through the circuit board at each chip contact location. This, in turn, makes it impractical to mount a chip onto a multi-layer circuit panel. Moreover, where the process is performed using an evaporative technique, the structure, including the chip and the circuit panel must be retained in the evaporation apparatus for the full time required to deposit the metal. Additionally, the resulting structure has no ability to take up differential expansion and contraction between the chip and the circuit panel. Thus, despite all of the effort in the art presented by the aforementioned patents and publications, further improvements in via formation and connection techniques would be desirable.
One aspect of the present invention provides a method of making connections in a microelectronic unit. A method according to this aspect of the invention includes the step of providing first and second conductive elements and a dielectric so that the dielectric and the conductive elements cooperatively define a substantially closed chamber. A dispersible conductive material, such as a metal having appreciable vapor pressure is also provided within the chamber. For example, low-melting metals such as tin, gallium, silver, indium and alloys thereof may be used. Other low-melting alloys include alloys containing one or more of tin, bismuth and antimony. The method further includes the step of dispersing the conductive material within the substantially closed chamber so that the conductive material deposits on the dielectric and forms a connector extending between the conductive elements. Most preferably, the step of dispersing the conductive material is performed by evaporating the conductive material within the chamber. The chamber desirably is maintained under subatmospheric pressure. Alternatively or additionally, the atmosphere within the chamber may consist essentially of one or more inert gases, most preferably argon. The dielectric, the conductive elements or both maintain the chamber substantially isolated from the surroundings during the dispersing step, so that the dispersing step occurs without appreciable transfer of the conductive material into the chambers during the dispersing step. Stated another way, the conductive material already present within the substantially closed chambers is dispersed in situ. Most preferably, the substantially closed chamber is sealed gas-tight by the conductive elements, the dielectric or both.
The step of providing first and second conductive elements and a dielectric may include providing a dielectric layer having oppositely directed first and second surfaces and having one or more holes extending through the layer between the surfaces, and providing the first and second conductive elements so that they overlie the hole on the first and second surfaces of the dielectric layer. For example, the first conductive elements, the second conductive elements or both may be provided on separate bodies bearing these elements. These bodies may be laminated onto the dielectric layer, thereby forming one or more chambers as discussed above. The conductive material may be provided on the conductive elements as, for example, by depositing the conductive material through one or more techniques such as electroplating, electroless plating, sputtering, evaporation and chemical vapor deposition.
Once the chamber or chambers is or are closed, the process of evaporation simply requires maintaining the assembly at a suitable temperature for a sufficient time to allow the conductive material to redistribute itself within the chambers by evaporation. The assembly may be maintained under an external, surrounding subatmospheric pressure as, for example, by holding the assembly within a temporary housing or storage bin held at subatmospheric pressure so as to minimize mechanical stress on the assembly and minimize diffusion into the chamber or chambers. However, there is no need to maintain the assembly within specialized processing apparatus during the evaporation process. The evaporation process may occur, for example, within a simple oven or holding fixture.
Numerous connections can be formed simultaneously using these methods. For example, hundreds or thousands of connections can be formed between individual conductive elements of an assembly during a single evaporation step. The process is inherently reliable; provided that the conductive material is present and the conductive elements are exposed to the interior of the chamber, the conductive material will form a conductor connecting the conductive elements. Moreover, the evaporation process can be repeated after the assembly is tested to repair any defects detected during testing operation. If an assembly has defects, the assembly is simply recycled into the heating step, without further processing. Unlike conventional via-forming processes such as electroplating, the process according to this aspect of this invention works best with small holes. For example, holes having cross-sectional dimensions on the order of 60 micrometers or less, and more preferably 25 micrometers (about 0.001 inches) or less may be used successfully. The process thus lends itself well to fabrication of extremely compact, high density circuits.
A further process according to this aspect of the invention includes the step of providing a first dielectric layer having first and second surfaces and having a plurality of holes extending through such layer between the first and second surfaces and providing first conductive elements adjacent the first surface and second conductive elements adjacent to second surface so that these conductive elements are aligned with at least some of the holes. For example, the step of providing the first conductive element may include providing a first body having the conductive elements thereon juxtaposed with first surface of the dielectric layer. The second conductive elements may be provided on a similar, second body juxtaposed with the second surface of the dielectric layer. A method according to this aspect of the invention desirably further includes the step of providing a conductive material in at least some of the holes which have the first and second conductive elements aligned therewith and dispersing the conductive materials, preferably by evaporating the conductive materials, so as to form conductors interconnecting the first and second conductive elements which are aligned with at least some of the holes.
The process can be used to provide connections to a semiconductor chip or other microelectronic element having contacts on a front surface. Thus, the first body used in the aforementioned process may be a chip, an assemblage of plural discrete chips or an integral wafer incorporating numerous semiconductor chips. The dielectric layer may be provided on the contact-bearing front surface of the chip, assembly or wafer as by applying a curable adhesive to the front surface and bonding a preformed dielectric layer onto the adhesive or by applying the dielectric layer as a coating and curing and curing the coating. The holes may be formed in the dielectric layer in alignment with the contacts either before or after applying the dielectric later to the front surface. In this arrangement, the contacts on the microelectronic element serve as the first conductive elements. The second conductive elements may be provided on a circuit panel or other mounting substrate. In certain embodiments, the second conductive elements may include elongated conductors having fixed ends and free ends. The fixed ends are aligned with at least some of the hole sin the dielectric element. The free ends of the leads may be displaceable relative to the dielectric layer so that a second microelectronic element may be attached to the free ends of the elongated conductors and moved away from the dielectric layer so as to deform the conductors. Alternatively, the dielectric layer may include elongated lead regions having fixed ends and having free ends displaceable with respect to the remainder of the dielectric layer. At least some of the conductors desirably extend along these elongated lead regions so that the free end of each such elongated conductor is disposed adjacently free end of an associated lead region. Here again, a further microelectronic element may be assembled to the free ends of the leads and moved away from the first microelectronic element and dielectric layer to deform the leads. As further discussed below, such processes can provide semiconductor chip packages and mountings with the ability to take up relative movement caused by thermal effects.
At least one of the steps of providing first conductive elements, providing second conductive elements, and providing conductive material may be performed selectively so that the first conductive element, the second conductive element, or the conductive material is omitted at least some of the holes and hence no connection is made between first and second conductive elements at those holes. The process therefore can be used to form connections selectively. As discussed below, selective formation of conductive elements and/or selective application of conductive material can be achieved readily using known techniques such as selective plating or etching, screen printing and selective vapor deposition, as for example, using a mask to block vapor deposition in areas where deposition is not wanted.
According to a further variant, the process may incorporate the step of providing a stacked structure including one or more dielectric layers and plural layers of conductive elements separated from one another by these one or more dielectric layers. At least some of the conductive elements in different layers are aligned with one another at one or more sites and the dielectric layers have holes extending through them between the aligned conductive elements at at least some of the sites. Here again, a dispersible conductive material such as the aforementioned high-vapor pressure metals is supplied at at least some of the sites. After the stacked structure has been made, the conductive material is evaporated onto the walls of the holes in the dielectric layers to thereby form vertical connections between conductive elements. The conductive metal may be evaporated within holes in all of the stacked layers simultaneously.
The vertical connections are formed at only those sites where the conductive elements are aligned with one another; where the dielectric layer which is disposed between these aligned conductive elements has a hole in alignment with the conductive element and where the conductive material is provided. This method is particularly well-suited to manufacture of multi-layer circuitry. Thus, the one or more dielectric layers typically includes numerous dielectric layers. The vertical conductors extending through the stacked structure can be provided selectively by conducting any one of several steps selectively. For example, the step of providing holes in the dielectric layers may be performed selectively so that holes are provided at less than all of the sites. The holes may be disposed at locations of a regular grid pattern, but less than all of such locations may be provided with holes. Also, the step of applying the evaporable conductive material may be performed selectively. For example, where the conductive material is applied onto the conductive elements before stacking as, for example, where the conductive material is applied by plating, the conductive material may be applied selectively by masking areas where conductive material is not wanted before plating or by selectively etching away the conductive material using an etchant which does not attack the conductive elements substantially. Stated another way, the operations required to provide conductive material in a selective manner to less than all of the sites may involve only conventional procedures commonly used for applying metals in a controlled fashion in microelectronic circuit processing.
The layers of conductive elements may include first direction and second direction layers arranged in alternating order. The conductive elements in each first direction layer include elongated traces extending predominantly in a first horizontal direction whereas the conductive elements in each second direction layer have elongated traces extending predominantly in a second horizontal direction transverse to the first horizontal direction. The holes are desirably arranged at at lest some locations of a regular grid pattern corresponding to crossing points of the first direction and second direction traces. Such an arrangement provides complete flexibility in layout of the circuit. Moreover, because very small vias can be employed, there is no need to provide enlarged features at the crossing points.
In further variants, the conductive material may be dispersed within the chambers by processes which do not entail evaporation as, for example, by applying sonic energy to atomize the conductive material in a liquid state or to mechanically spread the liquid conductive material. Here again, the process desirably does not rely upon filling of the chamber or via with liquid. In still other variants, a conductive material precursor is provided within the closed chambers and reacts to form a conductive material within the closed chambers.